The invention relates to an input circuit for, for example, an A/D converter. Such an input circuit can be used in a video data acquisition and conversion chain incorporating the A/D converter.
The invention also relates to an A/D converter, a receiver, a multimedia apparatus and an information read-out arrangement.
The article xe2x80x9cFully Bipolar, 120-Msample/s 10-b Track-and-Hold Circuitxe2x80x9d by P. Vorenkamp and J. P. M. Verdaasdonk, IEEE JSSC, Vol. 27, No. 7, July 1992, pp. 988-992 describes a prior-art input circuit to be used in a video data acquisition and conversion chain. The analog video input signal is filtered and fed into a track-and-hold (T/H) circuit which carries out a sampling operation. The sampled analog video signal is fed into a data conversion and processing module consisting of an A/D converter, a digital signal processor (DSP), and a digital-to-analog (D/A) converter. The cited article mentions that the T/H circuit, which is used as a presampler in front of the A/D converter, improves the high-frequency performance of the A/D converter. Generally, if a sampling circuit is placed in front of a signal processor, the sampling circuit should have a performance which is commensurate with that of the signal processor. If the signal processor has a relatively high performance, in the case of, for example, a high-resolution A/D converter, the sampling circuit will be relatively complex and hence costly. If, in addition, the sampling circuit has to cope with high-frequency input signals, it will consume an appreciable amount of power.
U.S. Pat. 4,831,379 describes a prior-art A/D converter. The prior-art A/D converter comprises an array of 64 input amplifiers. Assuming that i is an integer ranging from 0 to 63, each amplifier Ai amplifies the difference between an analog input voltage and a corresponding reference voltage VRi to produce an amplified output voltage VAi. The amplified output voltages VA0-VA63 are processed in a folding array and an interpolation circuit to produce complementary signals VD0/VDN0. VD31/VDN31, from which signals an output circuit derives a digital output code. A signal processor may comprise a conversion circuit which converts an input signal into sub-ranging signals associated with different amplitude sub-ranges. The above-identified prior-art A/D converter is such a signal processor. In the prior-art A/D converter, the array of 64 input amplifiers converts the input signal into 64 sub-ranging signals, namely the amplified output voltages VA0. VA63. Each of the amplified output voltages VA0. VA63 is associated with an amplitude sub-range centered around the respective reference voltages VR0-VR63. A disadvantage of this known converter is that it has a high power dissipation to obtain the output voltages VA0-VA63.
The invention seeks, inter alia, to provide an input circuit for an A/D converter which, with respect to the prior art, has less power dissipation and a low harmonic distortion. To this end, a first aspect of the invention provides an input circuit. A second aspect of the invention provides an A/D converter Third, fourth and fifth aspects of the invention provide a receiver, a multimedia apparatus and an information read-out arrangement.
The invention takes the following aspects into consideration.
By combining the sub-ranging means with the output stage of the sampling means, power dissipation is substantially reduced.
By using the sub-ranging means, the high-frequency performance is also improved.
An embodiment of an input circuit according to the invention combines the resistor ladder of the sub-ranging means with the resistor (ladder) of the output stage, the power dissipation is reduced.
An embodiment of an input circuit according to the invention is an input circuit with complementary input signals decreases the sensitivity of the A/D converter to interfering signals.
The invention and additional features which may be optionally used to implement the invention to advantage will be apparent from and elucidated with reference to the examples described hereinafter and shown in the Figures.